1. Field of the Invention
This invention is related to the field of signal synchronization, more specifically to preventing propagation of metastable signals.
2. Description of the Related Art
Most circuits in today's digital systems are synchronous circuits. A synchronous circuit or system is characterized by a clock signal that is used to control operation of the system by synchronizing the various components/circuit elements of the system/circuit, including the operation of the system/circuit's memory/storage elements and latches. Ideally, in a synchronous system, every change in the respective logical levels of the system's storage components is simultaneous, following the level changes of the clock signal. The expectation is for the input signal into each storage element to have reached its final value before the next change in the clock signal occurs, to obtain a deterministic, predictable behavior of the system.
While running a digital system using a system clock may theoretically provide stable and predictable operation, there are certain conditions under which the operation of a synchronous digital system may yield unpredictable results. Many current digital systems are expansive and may be required to operate on more than a single clock signal. Each clock signal used in multi-clock system is characterized as representing its own clock domain. Often times signals from one clock domain need to be provided to portions of the system operating in a different clock domain. In this sense, the signal entering from one clock domain, considered the source clock domain, into another clock domain, considered the target clock domain, may be considered an asynchronous signal from the perspective of the target clock domain. Asynchronous signals, especially those entering storage elements with feedback paths, are prone to cause a condition referred to as metastable condition. Metastability is identified as an unstable electronic state (in a sense a very delicate equilibrium state) that can persist for an indefinite period of time. In digital systems, metastability typically describes a state that doesn't settle into a stable, defined logic value, i.e. a logic ‘0’ or a logic ‘1’ level within the time required for proper operation. This can result in various portions of the system, or even the entire system—depending on the signal path where the metastable condition first occurs—to enter and remain in an undefined state, producing unpredictable system behavior. Metastability is therefore considered a failure mode in most digital systems.
Although metastable states are not expected to occur in fully synchronous systems when the set-up and hold time specifications are satisfied, they are considered inherent in asynchronous digital systems and systems with more than one clock domain, as mentioned above. However, careful design techniques can often reduce failures caused by metastability. In digital circuits, latches and flip-flops are often susceptible to metastability. A flip-flop, for example, has two well-defined stable states, traditionally designated as logic ‘0’ and logic ‘1’ states, but under certain conditions the output of a flip-flop can hover between these two well defined states for longer than a clock cycle, in other words, the output of the flip-flop might become metastable. Most commonly, a flip-flop will traverse a point of metastability if its inputs change simultaneously, or almost simultaneously, that is, in close proximity to each other within a certain timing margin. In such cases, the flip-flop's setup and hold time requirements are in essentially violated. There is a high probability that a change in the input during the time from the setup to the hold time, when the input of the flip-flop is expected to remain stable, will cause the flip-flop to enter a metastable state.
Overall, where data travels from the output of a source flip-flop to the input of target flip-flop, metastability can be caused by at least one of two conditions. First, if the target clock has a different frequency than the clock used in operating the source flip-flop, the setup and hold time of the target flip-flop can be violated. Second, when the target and source clock have the same frequency, a phase alignment can cause the data to arrive at the target flip-flop during its setup and hold time. These conditions can result from fixed overhead or variations in logic delay times on the worst case path between the two flip flops, or variations in clock arrival times (clock skew), or yet other causes.
One way to alleviate these problems when crossing clock domains is the use of synchronizer circuits to prevent circuit outputs from remaining in a metastable state. Traditional synchronizer designs are based on a high-gain latch circuit as a resolution element, in which back-to-back inverters (in a feedback loop) are sized up, and used with very low threshold voltage (VTH) transistors. In general, to meet the required mean time to failure (MTTF), multiple stage flip-flops may be needed which increases the overall latency. In addition, high-gain latches can use a significant amount of power, and are prone to leakage current as well.